| sysreg.h (278684) | sysreg.h (278631) |
|---|---|
| 1/*- 2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> 3 * Copyright 2014 Michal Meloun <meloun@miracle.cz> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 10 unchanged lines hidden (view full) --- 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * | 1/*- 2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> 3 * Copyright 2014 Michal Meloun <meloun@miracle.cz> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 10 unchanged lines hidden (view full) --- 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * |
| 27 * $FreeBSD: stable/10/sys/arm/include/sysreg.h 278684 2015-02-13 17:53:11Z ian $ | 27 * $FreeBSD: stable/10/sys/arm/include/sysreg.h 278631 2015-02-12 19:45:07Z ian $ |
| 28 */ 29 30/* 31 * Macros to make working with the System Control Registers simpler. | 28 */ 29 30/* 31 * Macros to make working with the System Control Registers simpler. |
| 32 * 33 * Note that when register r0 is hard-coded in these definitions it means the 34 * cp15 operation neither reads nor writes the register, and r0 is used only 35 * because some syntatically-valid register name has to appear at that point to 36 * keep the asm parser happy. | |
| 37 */ 38 39#ifndef MACHINE_SYSREG_H 40#define MACHINE_SYSREG_H 41 42#include <machine/acle-compat.h> 43 44/* --- 121 unchanged lines hidden (view full) --- 166#define CP15_DCCALL p15, 0, r0, c7, c10, 0 /* Data cache clean all */ 167#endif 168#define CP15_DCCMVAC(rr) p15, 0, rr, c7, c10, 1 /* Data cache clean by MVA PoC */ 169#define CP15_DCCSW(rr) p15, 0, rr, c7, c10, 2 /* Data cache clean by set/way */ 170#if __ARM_ARCH == 6 171/* Only ARMv6: */ 172#define CP15_CP15DSB p15, 0, r0, c7, c10, 4 /* DSB */ 173#define CP15_CP15DMB p15, 0, r0, c7, c10, 5 /* DMB */ | 32 */ 33 34#ifndef MACHINE_SYSREG_H 35#define MACHINE_SYSREG_H 36 37#include <machine/acle-compat.h> 38 39/* --- 121 unchanged lines hidden (view full) --- 161#define CP15_DCCALL p15, 0, r0, c7, c10, 0 /* Data cache clean all */ 162#endif 163#define CP15_DCCMVAC(rr) p15, 0, rr, c7, c10, 1 /* Data cache clean by MVA PoC */ 164#define CP15_DCCSW(rr) p15, 0, rr, c7, c10, 2 /* Data cache clean by set/way */ 165#if __ARM_ARCH == 6 166/* Only ARMv6: */ 167#define CP15_CP15DSB p15, 0, r0, c7, c10, 4 /* DSB */ 168#define CP15_CP15DMB p15, 0, r0, c7, c10, 5 /* DMB */ |
| 174#define CP15_CP15WFI p15, 0, r0, c7, c0, 4 /* WFI */ | |
| 175#endif 176 177#if __ARM_ARCH >= 7 178/* From ARMv7: */ 179#define CP15_DCCMVAU(rr) p15, 0, rr, c7, c11, 1 /* Data cache clean by MVA PoU */ 180#endif 181 182#if __ARM_ARCH == 6 --- 19 unchanged lines hidden (view full) --- 202#define CP15_TLBIASID(rr) p15, 0, rr, c8, c7, 2 /* Invalidate unified TLB by ASID */ 203 204#if __ARM_ARCH >= 6 205/* From ARMv6: */ 206#define CP15_TLBIMVAA(rr) p15, 0, rr, c8, c7, 3 /* Invalidate unified TLB by MVA, all ASID */ 207#endif 208 209/* | 169#endif 170 171#if __ARM_ARCH >= 7 172/* From ARMv7: */ 173#define CP15_DCCMVAU(rr) p15, 0, rr, c7, c11, 1 /* Data cache clean by MVA PoU */ 174#endif 175 176#if __ARM_ARCH == 6 --- 19 unchanged lines hidden (view full) --- 196#define CP15_TLBIASID(rr) p15, 0, rr, c8, c7, 2 /* Invalidate unified TLB by ASID */ 197 198#if __ARM_ARCH >= 6 199/* From ARMv6: */ 200#define CP15_TLBIMVAA(rr) p15, 0, rr, c8, c7, 3 /* Invalidate unified TLB by MVA, all ASID */ 201#endif 202 203/* |
| 210 * CP15 C9 registers 211 */ 212#if __ARM_ARCH == 6 && defined(CPU_ARM1176) 213#define CP15_PMCCNTR(rr) p15, 0, rr, c15, c12, 1 /* PM Cycle Count Register */ 214#elif __ARM_ARCH > 6 215#define CP15_PMCR(rr) p15, 0, rr, c9, c12, 0 /* Performance Monitor Control Register */ 216#define CP15_PMCNTENSET(rr) p15, 0, rr, c9, c12, 1 /* PM Count Enable Set Register */ 217#define CP15_PMCNTENCLR(rr) p15, 0, rr, c9, c12, 2 /* PM Count Enable Clear Register */ 218#define CP15_PMOVSR(rr) p15, 0, rr, c9, c12, 3 /* PM Overflow Flag Status Register */ 219#define CP15_PMSWINC(rr) p15, 0, rr, c9, c12, 4 /* PM Software Increment Register */ 220#define CP15_PMSELR(rr) p15, 0, rr, c9, c12, 5 /* PM Event Counter Selection Register */ 221#define CP15_PMCCNTR(rr) p15, 0, rr, c9, c13, 0 /* PM Cycle Count Register */ 222#define CP15_PMXEVTYPER(rr) p15, 0, rr, c9, c13, 1 /* PM Event Type Select Register */ 223#define CP15_PMXEVCNTRR(rr) p15, 0, rr, c9, c13, 2 /* PM Event Count Register */ 224#define CP15_PMUSERENR(rr) p15, 0, rr, c9, c14, 0 /* PM User Enable Register */ 225#define CP15_PMINTENSET(rr) p15, 0, rr, c9, c14, 1 /* PM Interrupt Enable Set Register */ 226#define CP15_PMINTENCLR(rr) p15, 0, rr, c9, c14, 2 /* PM Interrupt Enable Clear Register */ 227#endif 228 229/* | |
| 230 * CP15 C10 registers 231 */ 232/* Without LPAE this is PRRR, with LPAE it's MAIR0 */ 233#define CP15_PRRR(rr) p15, 0, rr, c10, c2, 0 /* Primary Region Remap Register */ 234#define CP15_MAIR0(rr) p15, 0, rr, c10, c2, 0 /* Memory Attribute Indirection Register 0 */ 235/* Without LPAE this is NMRR, with LPAE it's MAIR1 */ 236#define CP15_NMRR(rr) p15, 0, rr, c10, c2, 1 /* Normal Memory Remap Register */ 237#define CP15_MAIR1(rr) p15, 0, rr, c10, c2, 1 /* Memory Attribute Indirection Register 1 */ --- 27 unchanged lines hidden --- | 204 * CP15 C10 registers 205 */ 206/* Without LPAE this is PRRR, with LPAE it's MAIR0 */ 207#define CP15_PRRR(rr) p15, 0, rr, c10, c2, 0 /* Primary Region Remap Register */ 208#define CP15_MAIR0(rr) p15, 0, rr, c10, c2, 0 /* Memory Attribute Indirection Register 0 */ 209/* Without LPAE this is NMRR, with LPAE it's MAIR1 */ 210#define CP15_NMRR(rr) p15, 0, rr, c10, c2, 1 /* Normal Memory Remap Register */ 211#define CP15_MAIR1(rr) p15, 0, rr, c10, c2, 1 /* Memory Attribute Indirection Register 1 */ --- 27 unchanged lines hidden --- |