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imx51_ipuv3_fbd.c (266152) imx51_ipuv3_fbd.c (266365)
1/*-
2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (c) 2012, 2013 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * Portions of this software were developed by Oleksandr Rybalko
7 * under sponsorship from the FreeBSD Foundation.
8 *

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24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 */
31#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (c) 2012, 2013 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * Portions of this software were developed by Oleksandr Rybalko
7 * under sponsorship from the FreeBSD Foundation.
8 *

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24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 */
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: stable/10/sys/arm/freescale/imx/imx51_ipuv3_fbd.c 266152 2014-05-15 16:11:06Z ian $");
32__FBSDID("$FreeBSD: stable/10/sys/arm/freescale/imx/imx51_ipuv3_fbd.c 266365 2014-05-17 22:00:10Z ian $");
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/bio.h>
37#include <sys/bus.h>
38#include <sys/conf.h>
39#include <sys/endian.h>
40#include <sys/kernel.h>

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185{
186
187 if (!ofw_bus_status_okay(dev))
188 return (ENXIO);
189
190 if (!ofw_bus_is_compatible(dev, "fsl,ipu3"))
191 return (ENXIO);
192
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/bio.h>
37#include <sys/bus.h>
38#include <sys/conf.h>
39#include <sys/endian.h>
40#include <sys/kernel.h>

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185{
186
187 if (!ofw_bus_status_okay(dev))
188 return (ENXIO);
189
190 if (!ofw_bus_is_compatible(dev, "fsl,ipu3"))
191 return (ENXIO);
192
193 device_set_desc(dev, "i.MX515 Image Processing Unit (FB)");
193 device_set_desc(dev, "i.MX5x Image Processing Unit v3 (FB)");
194
195 return (BUS_PROBE_DEFAULT);
196}
197
198static int
199ipu3_fb_attach(device_t dev)
200{
201 struct ipu3sc_softc *sc = device_get_softc(dev);
202 bus_space_tag_t iot;
203 bus_space_handle_t ioh;
194
195 return (BUS_PROBE_DEFAULT);
196}
197
198static int
199ipu3_fb_attach(device_t dev)
200{
201 struct ipu3sc_softc *sc = device_get_softc(dev);
202 bus_space_tag_t iot;
203 bus_space_handle_t ioh;
204 int err;
204 phandle_t node;
205 pcell_t reg;
206 int err;
207 uintptr_t base;
205
206 ipu3sc_softc = sc;
207
208
209 ipu3sc_softc = sc;
210
208 device_printf(dev, "\tclock gate status is %d\n",
209 imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT));
211 if (bootverbose)
212 device_printf(dev, "clock gate status is %d\n",
213 imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT));
210
211 sc->dev = dev;
212
213 sc = device_get_softc(dev);
214 sc->iot = iot = fdtbus_bs_tag;
215
214
215 sc->dev = dev;
216
217 sc = device_get_softc(dev);
218 sc->iot = iot = fdtbus_bs_tag;
219
216 device_printf(sc->dev, ": i.MX51 IPUV3 controller\n");
217
220 /*
221 * Retrieve the device address based on the start address in the
222 * DTS. The DTS for i.MX51 specifies 0x5e000000 as the first register
223 * address, so we just subtract IPU_CM_BASE to get the offset at which
224 * the IPU device was memory mapped.
225 * On i.MX53, the offset is 0.
226 */
227 node = ofw_bus_get_node(dev);
228 if ((OF_getprop(node, "reg", &reg, sizeof(reg))) <= 0)
229 base = 0;
230 else
231 base = fdt32_to_cpu(reg) - IPU_CM_BASE(0);
218 /* map controller registers */
232 /* map controller registers */
219 err = bus_space_map(iot, IPU_CM_BASE, IPU_CM_SIZE, 0, &ioh);
233 err = bus_space_map(iot, IPU_CM_BASE(base), IPU_CM_SIZE, 0, &ioh);
220 if (err)
221 goto fail_retarn_cm;
222 sc->cm_ioh = ioh;
223
224 /* map Display Multi FIFO Controller registers */
234 if (err)
235 goto fail_retarn_cm;
236 sc->cm_ioh = ioh;
237
238 /* map Display Multi FIFO Controller registers */
225 err = bus_space_map(iot, IPU_DMFC_BASE, IPU_DMFC_SIZE, 0, &ioh);
239 err = bus_space_map(iot, IPU_DMFC_BASE(base), IPU_DMFC_SIZE, 0, &ioh);
226 if (err)
227 goto fail_retarn_dmfc;
228 sc->dmfc_ioh = ioh;
229
230 /* map Display Interface 0 registers */
240 if (err)
241 goto fail_retarn_dmfc;
242 sc->dmfc_ioh = ioh;
243
244 /* map Display Interface 0 registers */
231 err = bus_space_map(iot, IPU_DI0_BASE, IPU_DI0_SIZE, 0, &ioh);
245 err = bus_space_map(iot, IPU_DI0_BASE(base), IPU_DI0_SIZE, 0, &ioh);
232 if (err)
233 goto fail_retarn_di0;
234 sc->di0_ioh = ioh;
235
236 /* map Display Interface 1 registers */
246 if (err)
247 goto fail_retarn_di0;
248 sc->di0_ioh = ioh;
249
250 /* map Display Interface 1 registers */
237 err = bus_space_map(iot, IPU_DI1_BASE, IPU_DI0_SIZE, 0, &ioh);
251 err = bus_space_map(iot, IPU_DI1_BASE(base), IPU_DI0_SIZE, 0, &ioh);
238 if (err)
239 goto fail_retarn_di1;
240 sc->di1_ioh = ioh;
241
242 /* map Display Processor registers */
252 if (err)
253 goto fail_retarn_di1;
254 sc->di1_ioh = ioh;
255
256 /* map Display Processor registers */
243 err = bus_space_map(iot, IPU_DP_BASE, IPU_DP_SIZE, 0, &ioh);
257 err = bus_space_map(iot, IPU_DP_BASE(base), IPU_DP_SIZE, 0, &ioh);
244 if (err)
245 goto fail_retarn_dp;
246 sc->dp_ioh = ioh;
247
248 /* map Display Controller registers */
258 if (err)
259 goto fail_retarn_dp;
260 sc->dp_ioh = ioh;
261
262 /* map Display Controller registers */
249 err = bus_space_map(iot, IPU_DC_BASE, IPU_DC_SIZE, 0, &ioh);
263 err = bus_space_map(iot, IPU_DC_BASE(base), IPU_DC_SIZE, 0, &ioh);
250 if (err)
251 goto fail_retarn_dc;
252 sc->dc_ioh = ioh;
253
254 /* map Image DMA Controller registers */
264 if (err)
265 goto fail_retarn_dc;
266 sc->dc_ioh = ioh;
267
268 /* map Image DMA Controller registers */
255 err = bus_space_map(iot, IPU_IDMAC_BASE, IPU_IDMAC_SIZE, 0, &ioh);
269 err = bus_space_map(iot, IPU_IDMAC_BASE(base), IPU_IDMAC_SIZE, 0,
270 &ioh);
256 if (err)
257 goto fail_retarn_idmac;
258 sc->idmac_ioh = ioh;
259
260 /* map CPMEM registers */
271 if (err)
272 goto fail_retarn_idmac;
273 sc->idmac_ioh = ioh;
274
275 /* map CPMEM registers */
261 err = bus_space_map(iot, IPU_CPMEM_BASE, IPU_CPMEM_SIZE, 0, &ioh);
276 err = bus_space_map(iot, IPU_CPMEM_BASE(base), IPU_CPMEM_SIZE, 0,
277 &ioh);
262 if (err)
263 goto fail_retarn_cpmem;
264 sc->cpmem_ioh = ioh;
265
266 /* map DCTEMPL registers */
278 if (err)
279 goto fail_retarn_cpmem;
280 sc->cpmem_ioh = ioh;
281
282 /* map DCTEMPL registers */
267 err = bus_space_map(iot, IPU_DCTMPL_BASE, IPU_DCTMPL_SIZE, 0, &ioh);
283 err = bus_space_map(iot, IPU_DCTMPL_BASE(base), IPU_DCTMPL_SIZE, 0,
284 &ioh);
268 if (err)
269 goto fail_retarn_dctmpl;
270 sc->dctmpl_ioh = ioh;
271
272#ifdef notyet
273 sc->ih = imx51_ipuv3_intr_establish(IMX51_INT_IPUV3, IPL_BIO,
274 ipuv3intr, sc);
275 if (sc->ih == NULL) {

--- 74 unchanged lines hidden --- 		285 if (err)
286 goto fail_retarn_dctmpl;
287 sc->dctmpl_ioh = ioh;
288
289#ifdef notyet
290 sc->ih = imx51_ipuv3_intr_establish(IMX51_INT_IPUV3, IPL_BIO,
291 ipuv3intr, sc);
292 if (sc->ih == NULL) {

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